High voltage (HV) integrated circuits used in power management, power conversion, LCD/display, automotive and other applications typically operate between 52 V and 100 V. Stacked field effect transistor (FET) based cell structures are often used in the design of HV circuits. An occurrence of an electrostatic discharge (ESD) can severely and irreparably damage unprotected electronic circuits, including HV integrated circuits. As such, many HV integrated circuit chips may include a built-in ESD device to pro vide some measure of protection against the undesirable flow of damage-causing currents.
An ESD protection device in HV applications is typically prone to latch up errors since the FET operating voltages may exceed its design window (typically between supply voltage (VDD) and device breakdown voltage (BVDSS)). Stacking FET cell device (e.g., NMOS type) adds-up trigger voltage as well as the holding voltage by a factor N, where N is the number of devices being stacked. That is, although the stacking arrangement of N FET's has the potential to provide a total holding voltage of N times the holding voltage of each cell but it also provides a much higher trigger voltage (typically higher than BVDSS) which defeats the primary purpose of an ESD device since the protection feature is unable to be triggered before device breakdown.
From the foregoing discussion, it is desirable to provide tools and techniques to improve the robustness and reliability of ESD protection circuits in HV applications.